RF passive circuit and RF amplifier with via-holes

ABSTRACT

An input matching parallel inductor  114  which utilizes a spiral inductor, and an input matching parallel capacitor  115  which utilizes an MIM capacitor, both being constituting elements of an input matching circuit portion  125,  form an input matching parallel capacitor  115  inside an input matching circuit via-hole  121  being formed by applying a method of surface via-hole to the front surface of a GaAs substrate  124.  A choke inductor  119  which utilizes a spiral inductor, and a bypass capacitor  120  which utilizes an MIM capacitor, both being constituting elements of a drain voltage feeding circuit  107,  form a bypass capacitor  120  inside a drain voltage feeding circuit via-hole  123  formed by applying a method of surface via-hole to the front surface of the GaAs substrate  124.  A drain voltage terminal  136  is extended by a drawing wire  135  from between the spiral inductor and the drain voltage feeding circuit via-hole  123.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] This invention relates to a technology for making smaller andlighter RF passive circuits and RF amplifiers equipped with via-holes.

[0003] (2) Prior Art

[0004] Recently, various types of mobile communication tools, such asportable phones or portable information terminals have beencommercialized all over the world. As portable phones, cellular phonesfor bands of 900 MHz and 1.5 GHz, and Personal Handyphone System (PHS)for a band of 1.9 GHz are two examples that are commercialized inJapanese market. Other examples include world-famous GSM, and CDMA amongthe technologies adopted in PCS (Personal Communications Services) inthe U.S.A.

[0005] As a third-generation mode following the analogue mode and thedigital mode, IMT2000 is planned to be commercialized in the future.

[0006] In developing mobile communication terminals especially portableterminals, it is an inevitable trend to seek smaller and lighterterminals. Accordingly, it is important to achieve a technology formaking smaller and lighter components for these terminals.

[0007] As a trend, it is desired to make high frequency components ofthe portable terminals as a monolithic microwave IC (MMIC). The MMIC, inwhich active elements, their matching circuits, and bias circuits areintegrated on the same substrate, is more advantageous in making smallerproducts than a Hybrid IC which is structured to have circuits and biaselectricity-feeding circuits as outside-chips.

[0008] Even using the MMIC, it is required to ground circuit elements.Conventional grounding methods include a method of wire-bonding from thesurface of semiconductor substrates, and a via-hole method. It is moreeffective to use the via-hole method in achieving high-quality and lowcost for packaging, which makes the via-hole method more frequentlyadopted in the MMIC.

[0009] The following is a description of an example of a conventionaltype of RF passive circuit and RF amplifier equipped with via-holes withreference to FIGS. 8A-8D.

[0010]FIG. 8A is a schematic circuit diagram of a conventional RFamplifier which includes RF passive circuits equipped with via-holes,and FIG. 8B and 8C are pattern diagrams of conventional RF passivecircuits both equipped with a via-hole.

[0011] As FIG. 8A shows, a source-ground type of RF amplifier isconstructed by connecting: a gate bias resistance 805 and an inputmatching circuit 806 to a gate terminal 802; a drain voltage feedingcircuit 807 and an output matching circuit 808 to a drain terminal 803;and a source terminal 804 to a ground terminal 809, in the fieldeffective transistor (FET) 801. An input terminal 810 and an outputterminal 811 are both 50 Ω impedance, and the input matching circuit 806and the output matching circuit 808 are adjusted to 50 Ω. Further, eachof an input DC cut capacitor 812 and an output DC cut capacitor 813 isinserted to the input side and the output side respectively.

[0012] The input matching circuit 806 consists of an input matchingparallel inductor 814, an input matching parallel capacitor 815, and aninput matching serial inductor 816. The input matching parallelcapacitor 815 is grounded by an input matching circuit via-hole 821.

[0013] The output matching circuit 808 consists of an output matchingserial inductor 817, and an output matching parallel capacitor 818. Theoutput matching parallel capacitor 818 is grounded by an output matchingcircuit via-hole 822.

[0014] The drain voltage feeding circuit 807 consists of a chokeinductor 819 and a bypass capacitor 820. The bypass capacitor 820 isgrounded by a drain voltage feeding circuit via-hole 823.

[0015]FIGS. 8B and 8C are both pattern diagrams of an RF passive circuitwith a via-hole; each of them shows the input matching circuit 806 andthe drain voltage feeding circuit 807 respectively. FIG. 8D shows across-sectional view taken along line (A-A′) of FIG. 8B. The followingis a description of a common part between the input matching circuit 806and the drain voltage feeding circuit 807, taking an example of theinput matching circuit 806.

[0016] Constituting elements of the aforementioned input matchingcircuit 806 is made, as a semiconductor substrate, on a surface of aGaAs substrate 824. Both of the input matching parallel inductor 814 andthe input matching serial inductor 816 are made in aspiral-electrode-pattern, and the input matching parallel capacitor 815is made in an MIM(Metal-Insulator-Metal) capacitor pattern.

[0017] As FIG. 8D shows, the spiral-electrode-pattern is made on theGaAs substrate 824 which is covered by an insulator film 834 such assilicon oxide. Specifically, the spiral-electrode-pattern is a structurewhere a lower wiring metal layer 831 which is made by gold/titaniumvacuum evaporation is connected to an upper wiring metal layer 830 madeby gold-plating by means of a contact hole 833, with a between-layerinsulator film 832 in between.

[0018] On the other hand, the MIM capacitor is a structure where anupper wiring metal 829 is formed on a dielectric layer 828 under whichis an electrode extended from the lower wiring metal layer 831; theupper wiring metal 829 is made by gold/titanium vacuum evaporation andthe dielectric layer 828 is titanium oxide strontium (SrTiO3:STO) with apermittivity of 100 or more. The end of the electrode extended from theupper wiring metal 829 is connected to a ground metal layer 826 which issituated on the via-hole, as FIGS. 8B and 8C show.

[0019] The input matching circuit via-hole 821 can be formed by etchingfrom the main surface of the GaAs substrate 824 where circuit elementswere made (a surface via-hole). Or, it could also be formed by etchingfrom the other main surface (a backside via-hole). Inside the via-hole821, an electric conducting film is conducted to a backside ground metal829. This electric conducting film is electrically connected to theupper wiring metal 829 of the MIM capacitor through the ground metallayer 826.

[0020] Further, as depicted in FIG. 8C, constituting elements of thedrain voltage feeding circuit 807 are formed, as a semiconductorsubstrate, on the surface of the GaAs substrate 824. As for the chokeinductor 819, a spiral-electrode-pattern is used, and as for the drainvoltage feeding circuit via-hole 823, either a surface via-hole or abackside via-hole is used for forming.

[0021] Note that a feeding terminal 825 is structured by extending adrain voltage terminal 836 from the lower wiring metal layer 831 throughan extending wire 835.

[0022] Thus structured as above, the following constituting elements ofthe RF passive circuit are formed on and through the GaAs substrate: thespiral inductor, the MIM capacitor, and the via-hole. Moreover, as FIG.8C shows, the above three elements are positioned at a differentlocation two-dimentionally, and are connected to each other by wiring.The elements constitute the RF amplifier with a help of the inputmatching circuit 808 and the drain voltage feeding circuit 807.

[0023] As seen above, the conventional type of RF amplifiers and RFpassive circuits cannot be made smaller in size, due to thetwo-dimensional positioning of the constituting elements of the drainvoltage feeding circuit 807, which inherently take much space.

SUMMARY OF THE INVENTION

[0024] Based on the stated problem, the object of the present inventionis to realize smaller RF passive circuits and RF amplifiers equippedwith via-holes.

[0025] To achieve the above object, the present invention ischaracterized by a structure of being equipped with a spiral inductorformed on a main surface of a semiconductor substrate, and a via-holemade from the main surface and through the semiconductor substrate. Thevia-hole is made at the position adjacent to the spiral inductor, with adielectric layer and a wiring metal layer formed on a metal film of thevia-hole so as to hold a capacity element between the metal film and thewiring metal layer, and the spiral inductor extends at one end to beelectrically connected with the wiring metal layer.

[0026] The above structure enables to incorporate a capacitor in avia-hole, thereby enabling a three-dimensional location of the followingthree elements on one semiconductor substrate; a spiral inductor, acapacitor, and a via-hole. Thus reduced occupancy will produce an effectof enabling a smaller RF passive circuit and an RF amplifier made of theRF passive circuits as main components.

[0027] Furthermore, the RF amplifier of the present invention ischaracterized by a structure of utilizing the RF passive circuitequipped with the via-hole as a matching circuit, or as an RF choke in abias feeding circuit.

[0028] Furthermore, an RF passive circuit of the present invention isequipped with a spiral inductor formed on a main surface of asemiconductor substrate and a via-hole that is made from the mainsurface and goes through the semiconductor substrate. The via-hole isplaced adjacent to the spiral inductor, and on a metal film of thevia-hole, a first dielectric layer, a first wiring metal layer, a seconddielectric layer, and a second wiring metal layer are formed in thisorder, so as to form a first capacity element between the metal film ofthe via-hole and the first wiring metal layer, and a second capacityelement between the first wiring metal layer and the second wiring metallayer. The present invention is further structured to have the metalfilm and the second wiring metal layer electrically connected so as tohold a static capacity determined by a sum of the first capacity elementand the second capacity element. The present invention is furthercharacterized by a spiral inductor extending at one end to beelectrically connected to the first wiring metal layer.

[0029] This structure will help to make a smaller RF passive circuit anda smaller RF amplifier by enabling a three-dimensional location of aspiral inductor, a capacitor, and a via-hole. Moreover, a staticcapacity will be increased without increasing the occupancy, which willfacilitate designing of such a circuit as a bias feeding circuit of anRF amplifier which inherently requires large capacity.

[0030] In addition, the RF amplifier of the present invention ischaracterized by utilizing the RF passive circuit equipped with avia-hole as a matching circuit, or as an RF choke of a bias feedingcircuit.

[0031] Moreover, the RF passive circuit equipped with a via-hole ischaracterized by a metal film of the via-hole provided through a mainsurface of a semiconductor substrate which further extends along themain surface, and by a spiral metal layer formed on the extended part ofthe metal film, which works as an inductor with a dielectric layer inbetween. Here, the extended part of the metal film can be made in thesame spiral pattern as the spiral inductor which is formed on the metalfilm.

[0032] The above structure enables to accommodate a static capacitywhere the extended part of the metal layer and the spiral metal layerface each other with a dielectric layer in between. This realizes athree-dimensional location of a spiral inductor, a capacitor, and avia-hole, thereby reducing the occupancy thereof. This also helps tomake a smaller RF passive circuit, and a smaller RF amplifier.

[0033] Moreover, the RF amplifier of the present invention ischaracterized by utilizing the RF passive circuit equipped with avia-hole as a matching circuit, or as an RF choke of a bias feedingcircuit.

[0034] In addition, the RF passive circuit equipped with a via-hole thatthe present invention is applied to, is characterized by making avia-hole that goes through a semiconductor substrate, and by making adielectric layer so as to cover a metal film of the via-hole which isprovided through a main surface of the semiconductor substrate, and byan inductor formed as a spiral metal layer which covers the dielectriclayer so as to face against the metal film at one part, where a capacityelement is held between the via-hole and the inductor.

[0035] The above structure enables a three dimensional location of aspiral inductor, a capacitor, and a via-hole from inside to the surfaceof the semiconductor substrate, thereby reducing the occupancy thereof,and helps to make a smaller RF passive circuit and a smaller RFamplifier.

[0036] In addition, the RF amplifier of the present invention ischaracterized by utilizing an RF passive circuit equipped with avia-hole as a matching circuit, or as an RF choke of a bias feedingcircuit.

[0037] Moreover, the RF passive circuit with a via-hole that the presentinvention is applied to, is characterized by being equipped with avia-hole that goes through a semiconductor substrate from the other mainsurface of the semiconductor substrate, and by having a dielectric layeron a metal film of a via-hole provided through the main surface of asemiconductor substrate, and having a metal layer on the dielectriclayer, and holding a capacity element between the metal film of thevia-hole and the metal layer.

[0038] The above structure realizes a three dimensional location of acapacitor and a via-hole on one semiconductor substrate, therebyreducing the occupancy thereof. This realizes a smaller RF passivecircuit and a smaller RF amplifier.

[0039] In addition, the RE amplifier of the present invention ischaracterized by electrically connecting a wiring metal layer of the REpassive circuit with a gate terminal of a common gate circuit of a EET,or with a base terminal of a common base circuit of a bipolartransistor, or by electrically connecting, with a source terminal of aFET, a terminal which is a terminal of a resistance element electricallyconnected to the metal layer, so as to form a self bias circuit.

[0040] In addition, the RF passive circuit of the present inventionequipped with a via-hole is characterized by making a via-hole that goesthrough a semiconductor substrate, and by forming a dielectric layer anda wiring metal layer on a metal film of the via-hole, in this order, soas to hold a capacity element between a ground metal layer and thewiring metal layer.

[0041] The above structure enables a three dimensional location of acapacitor and a via-hole on one semiconductor substrate, therebyreducing the occupancy thereof. This helps making a smaller RF passivecircuit and a smaller RF amplifier.

[0042] Moreover, the RF amplifier of the present invention ischaracterized by electrically connecting a wiring metal layer of the RFpassive circuit with a gate terminal of a common gate circuit of a FET,or by electrically connecting the wiring metal layer with a baseterminal of a common base circuit in a bipolar transistor, or byconnecting a terminal of a resistance element of the RF passive circuitwith the ground metal layer, and the other terminal to the wiring metallayer, so as to form a self bias circuit.

[0043] The RF passive circuit equipped with a via-hole that the presentinvention is applied to, is further characterized by making a via-holethat goes through a semiconductor substrate, and by forming, on a metalfilm of the via-hole, a first dielectric layer, a first wiring metallayer, a second dielectric layer, and a second wiring metal layer inthis order. The RF passive circuit of the present invention is furthercharacterized by having a first capacity element between the metal filmand the first wiring metal layer, and the second capacity elementbetween the first wiring metal layer and the second wiring metal layer,and by electrically connecting the metal film and the second wiringmetal layer, so as to form a static capacity determined by a sum of thefirst capacity element and the second capacity element.

[0044] The RF amplifier of the present invention is furthercharacterized by electrically connecting a first wiring metal layer ofan RF passive circuit equipped with a via-hole with a gate terminal of acommon gate circuit of a FET, or by electrically connecting a firstwiring metal layer with a base terminal of a common base circuit of abipolar transistor. Or the RF amplifier is characterized by electricallyconnecting one terminal of a resistance element with the metal film, andthe other terminal with the first wiring metal layer, and the terminalof the resistance element which is electrically connected with thesecond wiring metal layer is further electrically connected with asource terminal of the FET so as to form a self bias circuit.

DESCRIPTION OF THE DRAWINGS

[0045] These and other objects, advantages and features of the inventionwill become apparent from the following description thereof taken inconjunction with the accompanying drawings which illustrate a specificembodiment of the invention. In the drawings:

[0046] FIGS. 1A-1D show an RF passive circuit and an RF amplifierequipped with via-holes according to the first embodiment of the presentinvention. FIG. 1A is a schematic circuit diagram that the RF passivecircuit of the present invention is applied to. FIG. 1B is a plan viewshowing an electrode pattern constituting a matching circuit which isone example of the RF passive circuit, and FIG. 1C is a plan viewshowing an electrode pattern constituting a bias feeding circuit whichis another example of the RF passive circuit. Finally FIG. 1D is across-sectional view of FIG. 1B.

[0047] FIGS. 2A-2D show an RF passive circuit and an RF amplifierequipped with via-holes according to the second embodiment of thepresent invention. FIG. 2A is a schematic circuit diagram that the RFpassive circuit of the present invention is applied to. FIG. 2B is aplan view showing an electrode pattern constituting a matching circuitwhich is one example of the RF passive circuit, and FIG. 2C is a planview showing an electrode pattern constituting a bias feeding circuitwhich is another example of the RF passive circuit. Finally FIG. 2D is across-sectional view of FIG. 2B.

[0048] FIGS. 3A-3C show an RF passive circuit and an RF amplifierequipped with via-holes according to the third embodiment of the presentinvention. FIG. 3A is a schematic circuit diagram that the RF passivecircuit is applied to. FIG. 3B is a plan view showing an electrodepattern constituting a matching circuit which is one example of the RFpassive circuit, and FIG. 3C is a cross-sectional view of FIG. 3B.

[0049] FIGS. 4A-4D show an RF passive circuit and an RF amplifierequipped with via-holes according to the fourth embodiment of thepresent invention. FIG. 4A is a schematic circuit diagram that the RFpassive circuit of the present invention is applied to. FIG. 4B is aplan view showing an electrode pattern constituting a matching circuitwhich is one example of the RF passive circuit, and FIG. 4C is a planview showing an electrode pattern constituting a bias feeding circuitwhich is another example of the RF passive circuit. Finally FIG. 4D is across-sectional view of FIG. 4B.

[0050] FIGS. 5A-5D show an RF passive circuit and an RF amplifierequipped with via-holes according to the fifth embodiment of the presentinvention. FIGS. 5A-5C are schematic circuit diagrams of the RFamplifier respectively. FIG. 5D is a cross-sectional view of a passivecircuit formed on a GaAs substrate which is applied to each circuit inFIGS. 5A-5C.

[0051] FIGS. 6A-6C show an RF passive circuit and an RF amplifierequipped with via-holes according to the sixth embodiment of the presentinvention. FIGS. 6A and 6B are schematic circuit diagrams of the RFamplifier, and FIG. 6C is a cross-sectional view of a passive circuitformed on a GaAs substrate which is applied to each circuit in FIGS. 6Aand 6B.

[0052] FIGS. 7A-7C show an RF passive circuit and an RF amplifierequipped with via-holes according to the seventh embodiment of thepresent invention. FIGS. 7A and 7B are schematic circuit diagrams of theRF amplifier, and FIG. 7C is a cross-sectional view of a passive circuitformed on a GaAs substrate which is applied to each circuit in FIGS. 7Aand 7B.

[0053] FIGS. 8A-8D show a conventional type of RF passive circuit and RFamplifier equipped with via-holes. FIG. 8A is a schematic diagram. FIG.8B is a plan view showing a matching circuit formed on a substrate. FIG.8C is a plan view showing a bias feeding circuit formed on a substrate,and FIG. 8D is a cross-sectional view of FIG. 8C.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] The following is a description of RF passive circuits and RFamplifiers equipped with via-holes, which are the preferred embodimentsof the present invention, with reference to the drawings.

[0055] 1. First Embodiment

[0056] FIGS. 1A-1D are drawn to describe the first embodiment of thepresent invention.

[0057]FIG. 1A is a schematic circuit diagram of the RF amplifier and theRF passive circuit that the present invention is applied to. The circuitis basically the same as the one in FIG. 8A, with minor difference inreference numbers for parts and materials. Therefore description isomitted.

[0058]FIGS. 1B and 1C are both diagrams showing a plan view ofstructures realized by an input matching circuit portion 125 and a drainvoltage feeding circuit 107 in FIG. 1 (1), pertaining to the firstembodiment.

[0059]FIG. 1B is a plan view of the input matching circuit portion 125.An input matching parallel inductor 114 is in aspiral-electrode-pattern, and an input matching parallel capacitor 115is an MIM capacitor and is created inside an input matching circuitvia-hole 121, which is a surface via-hole made from the front surface ofthe GaAs substrate 124.

[0060] The following is a detailed description of the above-mentionedstructure with reference to FIG. 1D, a cross-sectional diagram. Thewhole back surface of the GaAs substrate 124 is covered by the backsurface metal layer 127, and an insulator layer 134 is formed such assilicon oxide on an arbitrary part on the front surface of the GaAssubstrate 124. On the front surface of the GaAs substrate 124 where theinsulator layer 134 is not present, a via-hole 121 is formed by etching.On the insulator layer 134, a lower wiring metal layer 131 made bygold-plating is formed in a spiral pattern, which is covered by abetween-layer insulator film 132 made of silicon nitride. This is thencovered by an upper wiring metal layer 130 made by gold/titaniumplating. As FIG. 1B shows, the upper wiring metal layer 130 is in alinear form. The upper wiring metal layer 130 and the lower wiring metallayer 131 are connected to each other by a contact hole 133 goingthrough the between-layer insulator film 132. Both metal layers, puttogether, constitute the input matching parallel inductor 114equivalently.

[0061] The inside of the via-hole 121 is covered with a three-layer filmmade of: a ground metal layer 126, a dielectric layer 128, a firstwiring metal layer for capacity element 129, from the bottom. The groundmetal layer 126 contacts the back surface metal layer 127 on the bottomof the via-hole and it extends along the edge of the via-hole on thefront surface of the GaAs substrate. The dielectric layer 128 is made ofsuch material as titanium oxide strontium (SrTiO3: STO) whosepermittivity is 100 or more. The first wiring metal layer for capacityelement 129 extends on the between-layer insulator film 132 so as tomerge with the upper wiring metal layer 130. The three-layer film formsthe input matching parallel capacitor 115, which has a static capacitydetermined by the following elements: a permittivity of the dielectriclayer 128, the space between the two metal layers 126 and 129, and thedistance between the two layers.

[0062] The drain voltage feeding circuit 107 is structured basically thesame as the input matching circuit depicted in FIG. 1B. The onlydifference is that a drain voltage terminal 136 is drawn from between aspiral inductor and a drain voltage feeding circuit via-hole 123 througha drawing wire 135. Further explanation is omitted accordingly.

[0063] The above structure, incorporating a capacitor into a via-hole,is more advantageous in making smaller terminals than conventional onethat positions each element in different places.

[0064] Note that such devices as a bipolar trangister and a metal-oxidesemiconductor field-effect transistor (MOSFET) are to be alternativelyused as an active element of an RF amplifier.

[0065] Also note that although the description is confined to RFamplifiers, the present invention is applicable to other RF devices suchas mixer, or VCO, too.

[0066] 2. Second Embodiment

[0067] FIGS. 2A-2D are drawings depicted for the explanation of thesecond embodiment of the present invention. The application circuitswill not be described since they are the same as those of FIG. 1A. FIG.2B depicts an input matching circuit, and FIG. 2C depicts a drainvoltage feeding circuit. FIG. 2D is a cross-sectional view of bothcircuits.

[0068] The second embodiment has larger static capacity than the firstembodiment, realized by an input matching parallel capacitor 221 createdinside a via-hole 215. That is, the second embodiment has a five-layerfilm inside the via-hole 215 made by stacking: a ground metal layer 226,a first dielectric layer 2281, a first wiring metal layer for capacityelement 2291, a second dielectric layer 2282, and a second wiring metallayer for capacity element 2292, from the bottom. Note that the threemetal layers are made of the same metal material, which is the samematerial used in the first embodiment. Likewise, all the two dielectriclayers, in this second embodiment, are made of the same dielectricmaterial, which is the same material as the first embodiment. The fivelayers are connected in some parts; the first dielectric layer 2281 andthe second dielectric layer 2282 are connected at one end of both layersabove the GaAs substrate, over which the ground metal layer 226 and thesecond wiring metal layer for capacity element 2292 are connected.

[0069] This structure enables nearly twice as much space as the firstembodiment where the metal layers face each other, since both the groundmetal layer 226 and the second wiring metal layer for capacity element2292 are structured to face against the first wiring metal layer forcapacity element 2291. Therefore, if the permittivity of the dielectriclayer is the same, the static capacity will be nearly twice as large asthe first embodiment. Moreover, it does not damage the advantage inmaking smaller terminals since the total occupancy stays the same as thefirst embodiment.

[0070] 3. Third Embodiment

[0071] FIGS. 3A-3C are depicted for the explanation of the thirdembodiment.

[0072]FIG. 3A is a plan view showing a schematic circuit diagram for anRF amplifier the third embodiment is applied to. The circuits are thesame as those depicted in FIG. 8A, whose description is omittedaccordingly.

[0073]FIG. 3B shows a plan view of an input matching circuit portion 325and a drain voltage feeding circuit 307, both as parts of an RFamplifier of the third embodiment. FIG. 3C is a cross-sectional view ofFIG. 3B.

[0074] The following focuses on the input matching circuit portion 325for detailed description.

[0075] First, a first wiring metal layer 330 is formed by gold/titaniumvacuum evaporation in a spiral pattern seen from the above; it is formedso as to cover an insulator film 334 made of such materials as siliconoxide on a GaAs substrate 324. Next, a dielectric layer 328 made oftitanium oxide strontium which has a permittivity of 100 or more isapplied on the first wiring metal layer 330, in just about the same formas the first wiring metal layer 330, seen from the above. Then, thedielectric layer 328, in turn, is covered by a second wiring metal layer331 made by gold-plating or gold/titanium vacuum evaporation, also injust about the same form as the rest. The center of the spiral of thefirst wiring metal layer 330 is connected, at the end, to a ground metallayer 326 above the via-hole, and is grounded by the ground metal layer326 and the via-hole.

[0076] The third embodiment enables to have an input matching parallelcapacitor 315 since the first wiring metal layer 330 is structured toface the second wiring metal layer 331 with the dielectric layer 328 inbetween. Moreover with this embodiment, the second wiring metal layer331 is structured also to work as an inductor against high frequencies,as formed spirally and lengthy. Accordingly, the structure of FIGS. 3Band 3C, by grounding the capacitor at one end and connecting to aninductor at the other end, enables the input matching circuit portion325 and the drain voltage feeding circuit 307 equivalently.

[0077] 4. Fourth Embodiment

[0078] FIGS. 4A-4D are drawn to describe the fourth embodiment of thepresent invention.

[0079]FIG. 4A is a schematic circuit diagram for an RF passive circuitand an RF amplifier that this embodiment is applied to. The circuit inFIG. 4A is the same as FIG. 8A as self-explanatory, which does notprobably need further explanation.

[0080]FIGS. 4B and 4C are plan views showing an input matching circuitportion 425 and a drain voltage feeding circuit 407 respectively, bothshowing their circuit patterns, and FIG. 4D is a cross-sectional diagramthereof. The following description is confined to the input matchingcircuit portion, since it has many parts in common with the drainvoltage feeding circuit 407.

[0081] An input matching circuit via-hole 421 is placed underneath thecenter of the spiral of an input matching parallel inductor 414.

[0082] The input matching circuit via-hole 421 is made using a backsidevia-hole method from the back of the GaAs substrate 424. The groundmetal layer 426, made by gold-plating or gold/titanium vacuumevaporation, is on the via-hole 421 and is conducted to the backsideground metal layer 427.

[0083] On the ground metal layer 426, a dielectric layer 428 made oftitanium oxide strontium (SrTiO3:STO) with a permittivity of 100 or moreis formed, which has approximately the same form as the ground metallayer 426 seen from the above. On this dielectric layer 428, in turn, alower wiring metal 429 is formed by gold/titanium vacuum evaporation. AnMIM capacitor formed by the ground metal layer 426, the dielectric layer428, and the lower wiring metal 429 put together, makes an inputmatching parallel capacitor 415.

[0084] Around the MIM capacitor and on the GaAs substrate 424, abetween-layer insulator film 432 and an insulator film 434 made ofsilicon oxide for example are formed, which are then covered by an upperwire 430 in a spiral pattern made by such method as gold/titanium vacuumevaporation method. The center of the upper wire 430 is conducted to thelower wiring metal 429 via a contact hole 433. The upper wire 430 andthe lower wiring metal 429 form a spiral-formed inductor.

[0085] The fourth embodiment, just as the third embodiment, grounds oneend of the capacitor, while connecting the other end to the inductor,which forms equivalently the input matching circuit portion 425 depictedin FIG. 4A.

[0086] 5. Fifth Embodiment

[0087] FIGS. 5A-5D are drawn to describe the fifth embodiment of thepresent invention.

[0088]FIG. 5A shows a schematic circuit diagram of an RF amplifier thatthe fifth embodiment is applied to.

[0089] The RF amplifier depicted in FIG. 5A uses a common gate type FET.A bypass capacitor 536 and a gate voltage terminal 537 are connected toa gate terminal 502 of a FET 501; the bypass capacitor 536 is groundedby a ground via-hole 539. An input matching circuit 506 and a chokeinductor 540 are connected to a source terminal 504, and at the terminalof the choke inductor 540, a source voltage terminal 538 is connected. Adrain terminal 503 is connected to an output matching circuit 508, achoke inductor 519, and a bypass capacitor 520. An input terminal 510and an output terminal 511 are both 50 Ω impedance, and the inputmatching circuit 506 and the output matching circuit 508 are adjusted to50 Ω.

[0090] The structures described in the first, second, third, and fourthembodiments, are applicable to the input matching circuit 506 and theoutput matching circuit 508.

[0091]FIG. 5B is a schematic circuit diagram showing an RF amplifierusing a common base type bipolar transistor. A bypass capacitor 536 anda base voltage terminal 543 are connected to a base terminal 542 of abipolar transistor 541. The bypass capacitor 536 is grounded by theground via-hole 539. An input matching circuit 506 and a choke inductor540 are connected to an emitter terminal 544. At the terminal of thechoke inductor 540, an emitter voltage terminal 545 is connected.Finally an output matching circuit 508, a choke inductor 519, and abypass capacitor 520 are connected to a collector terminal 546. Both ofan input terminal 510 and an output terminal 511 are 50 Ω impedance, andboth of the input matching circuit 506 and the output matching terminal508 are adjusted to 50 Ω.

[0092] The structures described in the first, second, third, and fourthembodiments are applicable to the input matching circuit 506 and theoutput matching circuit 508.

[0093]FIG. 5C is a schematic circuit diagram showing an RF amplifierusing a source ground type FET which uses a self-bias method. A gatebias resistance 505 and an input matching circuit 506 are connected to agate terminal 502 of a FET 501. A self bias resistance 547 and a selfbias bypass capacitor 548 are connected to a source terminal 504, whichis grounded by a ground via-hole 538. Finally an output matching circuit508 a choke inductor 519, and a bypass capacitor 520 are connected to adrain terminal 503. An input terminal 510 and an output terminal 511 areboth 50 Ω impedance, and the input matching circuit 506 and the outputmatching circuit 508 are adjusted to 50 Ω.

[0094] The structures described in the first, second, third, and fourthembodiment are applicable to the input matching circuit 506 and theoutput matching circuit 508.

[0095]FIG. 5D is a cross-sectional view of a circuit patternconstituting a capacitor grounded by a via-hole at one end.

[0096] The ground via-hole 539 depicted in FIGS. 5A-5C is made by abackside via-hole method from the back of the GaAs substrate 524. Theground metal layer 526, made by gold-plating or gold/titanium vacuumevaporation, is conducted to the backside ground metal layer 527 of theGaAs substrate 524.

[0097] A dielectric layer 528 which is made of titanium oxide strontium(SrTiO3:STO) with a permittivity of 100 or more is formed on the groundmetal layer 526. On this dielectric layer 528, a wiring metal 529 isformed by such method as gold/titanium vacuum evaporation. A bypasscapacitor 536 and a self bias bypass capacitor 548 are formed using aMIM capacitor, which is obtained by combining the ground metal layer526, the dielectric layer 528, and the wiring metal 529.

[0098] The circuit structure depicted in FIGS. 5A and 5B is obtained byelectrically connecting the wiring metal 529 and the gate terminal 502.

[0099] Furthermore, the circuit structure in FIG. 5C is obtained byelectrically connecting one end of the self bias resistance 547 to thewiring metal 529, and the other end to the ground metal layer 526. Or,the circuit structure is alternatively obtained by using the insulatorlayer 534 formed around the dielectric layer 528 as a resistance layer,substituting it for the self bias resistance 547.

[0100] The fifth embodiment is structured to enable to make smallerterminals by placing the via-hole and the capacitor in the same positionon the substrate.

[0101] 6. Sixth Embodiment

[0102] FIGS. 6A-6C are drawn to explain the sixth embodiment.

[0103]FIG. 6A shows an RF amplifier that the sixth embodiment is appliedto.

[0104]FIGS. 6A and 6B are the same as FIGS. 5A and 5B respectively.Explanation of the circuit pertaining FIG. 6A and 6B is omittedaccordingly.

[0105] The circuit described in the first, second, third, and fourthembodiments of the present invention (i.e. FIGS. 1A, 2A, 3A, and 4A) isapplicable to an input matching circuit 606 and an output matchingcircuit 608.

[0106] A ground via-hole 638 depicted in FIGS. 6A-6C is formed by asurface via-hole method from the front surface of a GaAs substrate 624.Inside the ground via-hole 638, a bypass capacitor 636 and a self biasbypass capacitor 648 are formed. A ground metal layer 626 is formed, bygold-plating or gold/titanium vacuum evaporation, both inside and aroundthe via-hole on the GaAs substrate 624. The ground metal layer 626 isconducted to a backside ground metal layer 627 on the GaAs substrate624. A dielectric layer 628 made of titanium oxide strontium(SrTiO3:STO) which has a permittivity of 100 or more is formed on theground metal layer 626. On the dielectric layer 628, in turn, a firstwiring metal layer for capacity element 629 is formed by such method asa gold/titanium vacuum evaporation method. From the above, a bypasscapacitor 636 and a self bias bypass capacitor 648 are formed ascapacitor elements, by the ground metal layer 626, the first wiringmetal layer for capacity element 629, and the dielectric layer 628.

[0107] 7. Seventh Embodiment

[0108] FIGS. 7A-7C show the seventh embodiment of the present invention,which has a larger capacitor than the sixth embodiment.

[0109] The seventh embodiment is mostly the same as the sixth embodimentexcept how the capacitor is structured. The following descriptionfocuses on this point accordingly.

[0110] As FIG. 7C shows, a ground via-hole 738 is made from the frontsurface of a GaAs substrate 724 using a surface via-hole method, so asto form a bypass capacitor inside. A ground metal layer 726 is madeinside the ground via-hole 738 and also around the upper part thereof bygold-plating or gold/titanium vacuum evaporation. The ground metal layeris conducted to a backside ground metal layer 727. On the ground metallayer 726, a first dielectric layer 7281 is formed which is made oftitanium oxide strontium (SrTiO3:STO) with a permittivity of 100 ormore. Then, on this first dielectric layer 7281, a first wiring metallayer for capacity element 7291 is made by such method as gold/titaniumvacuum evaporation.

[0111] Further, on the first wiring metal layer for capacity element7291, a second dielectric layer 7282 is formed made of titanium oxidestrontium (SrTiO3:STO) with a permittivity of 100 or more, which is inturn covered by a second wiring metal layer for capacity element 7292made by such method as gold/titanium vacuum evaporation. Note that theground metal layer 726 and the second wiring metal layer for capacityelement 7292 are electrically connected.

[0112] The seventh embodiment is thus structured to create two capacityelements; the first capacity element by means of the ground metal layer726, the first wiring metal layer for capacity element 7291, and thefirst dielectric layer 7281; and the second capacity element by means ofthe first wiring metal layer for capacity element 7291, the secondwiring metal layer for capacity element 7292, and the second dielectriclayer 7282. From equivalent circuit point of view, a bypass capacitor iscreated by connecting the first capacity element and the second capacityelement in parallel (i.e. the capacity being a sum of the first and thesecond capacity elements).

[0113] Although the present invention has been fully described by way ofexamples with reference to the accompanying drawings, it is to be notedthat various changes and modifications will be apparent to those skilledin the art.

[0114] Therefore, unless such changes and modifications depart from thescope of the present invention, they should be construed as beingincluded therein.

What is claimed is:
 1. An RF passive circuit comprising: a semiconductorsubstrate; a spiral inductor which is formed on a main surface of thesemiconductor substrate; a via-hole which is formed at a positionadjacent to the spiral inductor by applying a metal film on an insidewall of a hole provided through the semiconductor substrate; adielectric layer which is formed on the metal film; and a wiring metallayer which is formed on the dielectric layer and holds a capacitorbetween the via-hole; wherein one end of the spiral inductor extends tobe connected with the wiring metal layer.
 2. The RF passive circuit ofclaim 1, wherein the spiral inductor has a double layer structure havingan upper wiring metal layer and a lower wiring metal layer, where atleast one of the wiring metal layers is in a spiral pattern, and wherethe wiring metal layers are connected to each other, with a contact holetherebetween.
 3. An RF choke used in at least one of a matching circuitand a bias feeding circuit, both circuits being included in an RFamplifier, the RF choke comprising: a semiconductor substrate where atleast one of the matching circuit and the bias feeding circuit isincorporated; a spiral inductor which is formed on a main surface of thesemiconductor substrate; a via-hole which is formed at a positionadjacent to the spiral inductor by applying a metal film on an insidewall of a hole provided through the semiconductor substrate; adielectric layer which is formed on the metal film; and a wiring metallayer which is formed on the dielectric layer and holds a capacitorbetween the via-hole, wherein one end of the spiral inductor extends tobe connected with the wiring metal layer.
 4. An RF passive circuitcomprising: a semiconductor substrate; a spiral inductor which is formedon a main surface of the semiconductor substrate; a via-hole which isformed at a position adjacent to the spiral inductor by applying a metalfilm on an inside wall of a hole provided through the semiconductorsubstrate; a first wiring metal layer which is formed on a firstdielectric layer and equivalently forms a first capacity element betweenthe via-hole; and a second wiring metal layer which is formed on thefirst wiring metal layer with a second dielectric layer therebetween,and equivalently forms a second capacity element between the firstwiring metal layer, wherein the via-hole and the second wiring metallayer are electrically connected to be able to hold a static capacitydetermined by a sum of the first capacity element and the secondcapacity element, and wherein one end of the spiral inductor furtherextends so as to be electrically connected to the first wiring metallayer.
 5. The RF passive circuit of claim 4, wherein the spiral inductorhas a double layer structure having an upper wiring metal layer and alower wiring metal layer, where at least one of the wiring metal layersis in a spiral pattern, and where the wiring metal layers are connectedto each other, with a contact hole therebetween.
 6. An RF choke used inat least one of a matching circuit and a bias feeding circuit, bothcircuits being included in an RF amplifier, the RF choke comprising: asemiconductor substrate where at least one of the matching circuit andthe bias feeding circuit is incorporated; a spiral inductor which isformed on a main surface of the semiconductor substrate; a via-holewhich is formed at a position adjacent to the spiral inductor byapplying a metal film on an inside wall of a hole provided through thesemiconductor substrate; a first wiring metal layer which is formed on afirst dielectric layer and equivalently forms a first capacity elementbetween the via-hole; and a second wiring metal layer which is formed onthe first wiring metal layer with a second dielectric layertherebetween, and equivalently forms a second capacity element betweenthe first wiring metal layer, wherein the via-hole and the second wiringmetal layer are electrically connected to be able to hold a staticcapacity determined by a sum of the first capacity element and thesecond capacity element, and wherein one end of the spiral inductorfurther extends so as to be electrically connected to the first wiringmetal layer.
 7. An RF passive circuit comprising: a semiconductorsubstrate; a via-hole which is formed by applying a metal film on aninside wall of a hole provided through the semiconductor substrate; awiring metal layer which is formed on a main surface of thesemiconductor substrate and is electrically connected to the via-hole;and an inductor which is made of a metal film in a spiral pattern and isformed on the first wiring metal layer with a dielectric layertherebetween.
 8. The RF passive circuit of claim 7, wherein the wiringmetal layer is in the same parallel pattern as the inductor.
 9. An RFchoke used in at least one of a matching circuit and a bias feedingcircuit, both circuits being included in an RF amplifier, the RF chokecomprising: a semiconductor substrate where at least one of the matchingcircuit and the bias feeding circuit is incorporated; a via-hole whichis formed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a wiring metal layer which isformed on a main surface of the semiconductor substrate and iselectrically connected to the via-hole; and an inductor which is made ofa metal film in a spiral pattern and is formed on the first wiring metallayer with a dielectric layer therebetween.
 10. An RF passive circuitcomprising: a semiconductor substrate; a via-hole which is formed byapplying a metal film on an inside wall of a hole provided through thesemiconductor substrate; a dielectric layer which is formed on a mainsurface of the semiconductor substrate so as to cover the metal film;and an inductor which is a spirally-formed metal layer formed on thedielectric layer, which forms a static capacity where one part thereoffaces the metal film of the via-hole.
 11. An RF choke used in at leastone of a matching circuit and a bias feeding circuit, both circuitsbeing included in an RF amplifier, the RF choke comprising: asemiconductor substrate where at least one of the matching circuit andthe bias feeding circuit is incorporated; a via-hole which is formed byapplying a metal film on an inside wall of a hole provided through thesemiconductor substrate; a dielectric layer which is formed on a mainsurface of the semiconductor substrate so as to cover the metal film;and an inductor which is a spirally-formed metal layer formed on thedielectric layer, which forms a static capacity where one part thereoffaces the metal film of the via-hole.
 12. An RF passive circuitcomprising: a semiconductor substrate; a dielectric layer which isformed on a first main surface of the semiconductor substrate; avia-hole which is formed by applying a metal film on an inside wall of ahole provided through a second main surface of the semiconductorsubstrate until the hole reaches the dielectric layer; and a metal layerformed on the dielectric layer which holds a static capacity between themetal film of the via-hole and the metal layer.
 13. The RF passivecircuit of claim 12, further comprising: a resistance element whose oneterminal is electrically connected to the metal layer, and the otherterminal to the via-hole.
 14. An RF amplifier comprising: asemiconductor substrate; a dielectric layer which is formed on a firstmain surface of the semiconductor substrate; a via-hole which is formedby applying a metal film on an inside wall of a hole provided through asecond main surface of the semiconductor substrate until the holereaches the dielectric layer; a metal layer formed on the dielectriclayer which holds a static capacity between the metal film of thevia-hole and the metal layer; and a field effective transistor, mountedon the semiconductor substrate, which has a common gate circuit having agate terminal electrically connected to the metal layer.
 15. An RFamplifier comprising: a semiconductor substrate; a dielectric layerwhich is formed on a first main surface of the semiconductor substrate;a via-hole which is formed by applying a metal film on an inside wall ofa hole provided through a second main surface of the semiconductorsubstrate until the hole reaches the dielectric layer; a metal layerformed on the dielectric layer which holds a static capacity between themetal film of the via-hole and the metal layer; and a bipolartransistor, mounted on the semiconductor substrate, which has a commonbase circuit having a base terminal electrically connected to the metallayer.
 16. An RF amplifier comprising: a semiconductor substrate; adielectric layer which is formed on a first main surface of thesemiconductor substrate; a via-hole which is formed by applying a metalfilm on an inside wall of a hole provided through a second main surfaceof the semiconductor substrate until the hole reaches the dielectriclayer; a metal layer formed on the dielectric layer which holds a staticcapacity between the metal film of the via-hole and the metal layer; aresistance element whose one terminal is electrically connected to thevia-hole and the other terminal to the metal layer; and a fieldeffective transistor mounted on the semiconductor substrate whose sourceterminal is connected to the other terminal of the resistance elementconnected to the metal layer, so as to form a self bias circuit.
 17. AnRF passive circuit comprising: a semiconductor substrate; a via-holewhich is formed by applying a metal film on an inside wall of a holeprovided through the semiconductor substrate; a dielectric layer whichis formed on an inside wall of the via-hole; and a wiring metal layerformed on the dielectric layer, which holds a static capacity betweenthe via-hole.
 18. The RF passive circuit of claim 17, furthercomprising: a resistance element whose one terminal is electricallyconnected to the metal film of the via-hole, and the other terminal tothe wiring metal layer.
 19. An RF amplifier comprising: a semiconductorsubstrate; a via-hole which is formed by applying a metal film on aninside wall of a hole provided through the semiconductor substrate; adielectric layer which is formed on an inside wall of the via-hole; awiring metal layer formed on the dielectric layer, which holds a staticcapacity between the via-hole; and a field effective transistor, mountedon the semiconductor substrate, which has a common gate circuit having agate terminal electrically connected to the wiring metal layer.
 20. AnRF amplifier comprising: a semiconductor substrate; a via-hole which isformed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a dielectric layer which is formedon an inside wall of the via-hole; a wiring metal layer formed on thedielectric layer, which holds a static capacity between the via-hole;and a bipolar transistor, mounted on the semiconductor substrate, whichhas a common base circuit having a base terminal electrically connectedto the wiring metal layer.
 21. An RF amplifier comprising: asemiconductor substrate; a via-hole which is formed by applying a metalfilm on an inside wall of a hole provided through the semiconductorsubstrate; a dielectric layer which is formed on an inside wall of thevia-hole; a wiring metal layer formed on the dielectric layer, whichholds a static capacity between the via-hole; a resistance element whoseone terminal is electrically connected to the metal film of the via-holeand the other terminal to the metal layer; and a field effectivetransistor mounted on the semiconductor substrate whose source terminalis connected to the other terminal of the resistance element connectedto the metal layer, so as to form a self bias circuit.
 22. An RF passivecircuit comprising: a semiconductor substrate; a via-hole which isformed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a first dielectric layer which isformed on an inside wall of the via-hole; a first wiring metal layerformed on the first dielectric layer which equivalently forms a firstcapacity element between the via-hole; a second dielectric layer whichis formed on the first wiring metal layer; and a second wiring metallayer formed on the second dielectric layer which equivalently forms asecond capacity element between the first wiring metal layer, whereinthe via-hole and the second wiring metal layer are electricallyconnected, and the sum of static capacity of the first capacity elementand the second capacity element are held between the via-hole and thefirst wiring metal layer.
 23. The RF passive circuit of claim 22,further comprising: a resistance element whose one terminal iselectrically connected either to the second wiring metal layer or to thevia-hole, and the other terminal to the first wiring metal layer.
 24. AnRF amplifier comprising: a semiconductor substrate; a via-hole which isformed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a first dielectric layer which isformed on an inside wall of the via-hole; a first wiring metal layerformed on the first dielectric layer which equivalently forms a firstcapacity element between the via-hole; a second dielectric layer whichis formed on the first wiring metal layer; a second wiring metal layerformed on the second dielectric layer which equivalently forms a secondcapacity element between the first wiring metal layer, the via-hole andthe second wiring metal layer being electrically connected, and the sumof static capacity of the first capacity element and the second capacityelement being held between the via-hole and the first wiring metallayer; and a field effective transistor, mounted on the semiconductorsubstrate, which has a common gate circuit having a gate terminalelectrically connected to the first wiring metal layer.
 25. An RFamplifier comprising: a semiconductor substrate; a via-hole which isformed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a first dielectric layer which isformed on an inside wall of the via-hole; a first wiring metal layerformed on the first dielectric layer which equivalently forms a firstcapacity element between the via-hole; a second dielectric layer whichis formed on the first wiring metal layer; a second wiring metal layerformed on the second dielectric layer which equivalently forms a secondcapacity element between the first wiring metal layer, the via-hole andthe second wiring metal layer being electrically connected, and the sumof static capacity of the first capacity element and the second capacityelement being held between the via-hole and the first wiring metallayer; and a bipolar transistor, mounted on the semiconductor substrate,which has a common base circuit having a base terminal electricallyconnected to the first wiring metal layer.
 26. An RF amplifiercomprising: a semiconductor substrate; a via-hole which is formed byapplying a metal film on an inside wall of a hole provided through thesemiconductor substrate; a first dielectric layer which is formed on aninside wall of the via-hole; a first wiring metal layer formed on thefirst dielectric layer which equivalently forms a first capacity elementbetween the via-hole; a second dielectric layer which is formed on thefirst wiring metal layer; a second wiring metal layer formed on thesecond dielectric layer which equivalently forms a second capacityelement between the first wiring metal layer, the via-hole and thesecond wiring metal layer being electrically connected, and the sum ofstatic capacity of the first capacity element and the second capacityelement being held between the via-hole and the first wiring metallayer; a resistance element whose one terminal is electrically connectedeither to the second wiring metal layer or to the via-hole, and theother terminal to the first wiring metal layer; and a field effectivetransistor mounted on the semiconductor substrate whose source terminalis connected to the one terminal of the resistance element connectedeither to the second wiring metal layer or to the via-hole, so as toform a self bias circuit.